Design of a digital filter bank based on hierarchical data-path resource-sharing on FPGAs (Thai)

Abstract

This paper presents a large digital circuit design methodology for a digital filter bank circuit on an area limited FPGA (Field Programmable Gate Array). The design is divided into two parts: a data-path part for data processing and a control part for controlling data-path operations. The data-path part is designed by using a hierarchical resource-sharing technique to reduce the circuit size. The set of functions describing the circuit behavior is translated into hierarchical data flow graphs (DFGs). Then the DFGs are hierarchically grouped into the same structure DFGs to share the same resources from large to small groups. The slower operation of the circuit after resource-sharing is of concern. In the control part, the FSM (Finite State Machine) in Moore machine format is used for controlling the correct sequence of the resource-sharing in the data-path part. The designed circuit was tested on a Xilinx FPGA SPARTAN-3 XCS4000-5FG676. The circuit worked correctly compared to the calculation results from MATLAB. From the synthesis results, the circuit size is 44% smaller, and the cycle time is 30% slower, compared to the original circuit without resource-sharing.